Integrated circuit architectures comprising complementary types of devices, such as the opposite conductivity type regions of CMOS circuit structures, may typically contain one polarity type of device in the semiconductor bulk, while a second polarity type of device is contained in a well region, the well region having a conductivity type opposite to that of the substrate in which the well is formed, so that the well region defines a PN junction with the opposite conductivity type semiconductor material of the bulk. An example of a CMOS circuit comprising this configuration is an inverter circuit, typically employed in present day digital/signal processing logic architectures, having opposite conductivity channel type transistors.
A schematic diagram of such a complementary channel type transistor logic circuit is shown in FIG. 1 as comprising an N channel MOS transistor 13 and a P channel MOS transistor 14. The gates of transistors 13 and 14 are connected in common to an input line 11, while the drain electrodes thereof are connected in common to an output electrode 12. The source of P channel transistor 14 is connected to the body of transistor 14 and to a positive polarity power supply (+V.sub.DD) link 15, while the source of N channel transistor 13 is connected to the body of transistor 13 and to a negative power supply (-V.sub.SS) link 16.
The semiconductor architectural configuration of the complementary MOS transistor pair of the circuit of FIG. 1 may be formed as a planar structure wherein field and gate oxide layers are formed atop an effectively planar substrate surface as illustrated in FIG. 2, or as a non-planar structure such as one employing local oxidation isolation as illustrated in FIG. 3.
In the planar configuration of FIG. 2, an N channel transistor 13 is disposed in a P-well region 23 that has been formed adjacent a top surface 21 of an N-type planar substrate 20. P-well region 23 forms a PN junction 22 with the N-type material of the substrate 20. Disposed in the P well region 23 are a pair of N+ regions 27 and 28 which form the respective source and drain regions of the N-channel transistor 13. Overlying the channel path between regions 27 and 28 is a thin layer of gate dielectric 41 (e.g. silicon dioxide), atop which is disposed a gate electrode layer 42. Also formed in P-well region 23 is a P+ well contact region 26. By way of respective openings or vias in a passivating dielectric (e.g. silicon dioxide) layer 25 disposed atop the surface 21 of substrate 20, electrode contacts 46 and 47 for regions 26 and 27 are provided. Each of these contacts is connected by way of a line 16 to one polarity (-V.sub.SS) of the power supply for the complementary transistor pair, as schematically illustrated in FIG. 1 and diagrammatically shown in FIG. 2.
The P channel transistor 14 is formed of a pair of P+ regions 37 and 38 disposed adjacent to surface 21 of substrate 20, proper, regions 37 and 38 respectively constituting the source and drain regions of the P channel transistor 14. Region 38 is connected by way of an overlying contact metallization layer 48 to the region 28 of the N channel transistor 13, and to output line 12. Source region 37 is coupled via contact 57 to power supply (+V.sub.DD) link 15 and, via contact metallization 56, to an N+ substrate contact region 36. A thin layer of gate dielectric material (e.g. gate oxide) 51 is disposed on the planar surface 21 overlying the channel path between regions 37 and 38 and a gate electrode layer 52 is provided on the gate dielectric layer 51. Gate electrode layers 42 and 52 of respective transistors 13 and 14 may comprise a metallic layer or a doped polysilicon layer. The respective gates of the transistors 13 and 14 are connected y way of gate contacts 43 and 53 to input link 11. If, on the other hand, and as is often the case, the gates are formed from one continuous line of gate material, only one contact to the input link is needed.
The embodiment of a non-planar structure shown in FIG. 3 is substantially the same as that of FIG. 2, except that, in place of field oxide layer 25 atop surface 21, a recessed dielectric isolation layer 35 has been formed, for example, by local oxidation. Layer 35 extends beneath the surface 21 of the substrate to provide oxide isolation adjacent the respective regions of the device structure.
One of the limitations of the CMOS architecture shown in FIGS. 2 and 3 is the surface occupation area or spacing between N+ drain region 28 of the N channel transistor 13 and P+ drain region 38 of the P channel transistor 14. More specifically, the N+ material of drain region 28 of N channel transistor 13 forms a PN junction 61 with the P material of P well region 23. Similarly, the P+ material of drain region 38 of P channel transistor 14 forms a PN junction 63 with the N-type material of substrate 20. Because of the creation of a depletion region which extends from these PN junctions towards the depletion region that extends from the PN junction 22 between the P well region 23 and the substrate 20, it is necessary to provide a spacing d2 between PN junction 63, defined between drain region 38 and the substrate 20, and the PN junction 22, defined between the well region 23 and the substrate 20, proper. Similarly, it is necessary to space the drain region 28 of the N-channel transistor 13, which forms a PN junction 61 with the P well region 23, from the PN junction 22 by a distance dl. These spacings d1 and d2 will be determined by the characteristics of the regions and the operational parameters of the device. What is important is that if the spacings dl and d2 are too small, the depletion regions which extend from PN junctions 22, 61 and 63 may touch each other, resulting in a shorting of the N+ drain region 28 of N channel transistor 13 to the N-substrate 20 and/or a shorting of the P+ drain region 38 of P channel transistor 14 with the P well region 23. Typically, spacings d1 and d2 are on the order of 1-4 .mu.m. As a result of this spacing constraint, the circuit occupation area of the CMOS structure is necessarily large. The large area, in turn, results in the length of the overall wiring for the integrated circuit structure containing such circuits and the parasitic effects associated with such wiring being quite large.